The present invention relates to an improvement of an initial value setting circuit, by which an operational condition of an internal circuit of a semiconductor integrated circuit can be univocally determined to a predetermined initial condition, in order to eliminate any erroneous operations of this internal circuit when the electric power unit is turned on.
FIG. 8 shows one example of a conventionally available initial value setting circuit, which will be explained in detail below.
In the initial value setting circuit of FIG. 8, reference numeral 50 represents an input terminal into which an initial-condition-reset signal is entered, and reference numeral 51 represents an N-channel MOS transistor connected to an electric power source Vcc. A gate of the N-channel MOS transistor 51 is connected to the input terminal 50. Reference numeral 52 represents a capacitor which receives electric charges supplied From the electric power source Vcc in response to a turning-on operation of the MOS transistor 51. Reference numeral 53 represents an output node which is in the same voltage level as a connecting point between the N-channel MOS transistor 51 and the capacitor 52. Reference numeral 54 represents a P-channel MOS transistor connected to the output node 53. A gate of the P-channel MOS transistor 54 is connected to the electric power source Vcc. Reference numeral 55 represents an inverter connected to the node 53.
Furthermore, reference numeral 60 represents a set & reset circuit, which comprises an output terminal 56, a signal line 57 whose operational condition (i.e. voltage level) is not univocally determined at the moment immediately after the electric power unit is turned on, and an OR circuit 58 interposed between the output terminal 56 and the signal line 57. Of two input terminals of OR circuit 58, one terminal is connected to the signal line 57 and the other terminal is connected to the output terminal of the inverter 55.
According to the conventional initial value setting circuit shown in FIG. 8, a voltage level of the input terminal 50, i.e. a voltage level of a processing condition reset signal, is in a low level when the electric power unit is turned on. Accordingly, the N-channel MOS transistor 51 is turned off. A voltage level of the output node 53 is in a low level due to capacity coupling of the capacitor 52. Thus, the inverter 55 generates an initial setting signal of high level. As a result, the set & reset circuit 60 generates a high-level voltage from its output terminal 56. Hence, a voltage level of an internal circuit of a semiconductor integrated circuit is set to a high level as an initial setting value. In this condition, the P-channel MOS transistor 54 is turned off under the application of the voltage of the electric power source Vcc.
Thereafter, when the voltage level of the input terminal 50 becomes a high level, the N-channel MOS transistor 51 is turned on to charge up the capacitor 52. Thus, the output node 53 is turned to a high level, and the output of the inverter 55 becomes a low level, thereby stopping generation of the initial setting signal of high level. As a result, the internal circuit of the semiconductor integrated circuit changes its operational condition in response to the voltage level of the signal line 57. After the reset of the above-described initial setting condition, the voltage level of the input terminal 50 is changed to a low level to turn off the N-channel MOS transistor 51, thereby stopping the charging of capacitor 52.
On the other hand, when the electric power unit is turned off, the gate voltage of the P-channel MOS transistor 54 becomes 0 v. Thus, the P-channel MOS transistor 54 is turned on. In response to the turning-on of the transistor 54, electric charge stored in the capacitor 52 is discharged through the P-channel MOS transistor 54 to the ground. Thus, the voltage level of the output node 53 is returned to the initial condition of low level.
However, the above-described conventional initial value setting circuit is defective in the following points. Namely, after the initial condition of the internal circuit of the semiconductor integrated circuit is reset (i.e. when the output node 53 is in a high level condition), electric charge stored in the capacitor 52 is reduced by leakage. If such leakage is increased, the voltage level of the output node 53 may be changed from high level to low level. For this reason, the inverter 55 will generate tile initial setting signal (high level), which turns the voltage level of the output terminal 56 of the set & reset circuit 60 to a high level. Hence, there is a problem that the internal circuit of the semiconductor integrated circuit may be erroneously set to a high level as an initial setting.
To solve this problem it will be, for example, possible to propose a modified initial value setting circuit shown in FIG. 9 as an improvement of FIG. 8 circuit.
The initial value setting circuit shown in FIG. 9 is basically different from FIG. 8 circuit in that the P-channel MOS transistor 54 is removed and a feedback transistor 70 constituted by a P-channel transistor is newly added.
The feedback transistor 70 is connected between the electric power source Vcc and the output node 53. A gate of the feedback transistor 70 is connected to the output terminal of the inverter 55. Accordingly, when the output node 53 is kept at a high level by electric charges stored in the capacitor 52, i.e. when the output of the inverter 55 is in a low level, the feedback transistor 70 is turned on. Thus, electric charge is supplied from she electric power source Vcc to the capacitor 52, thereby maintaining the output node 53 at a high level. Furthermore, when the electric power unit is turned off, electric charge stored in the capacitor 52 is discharged through the output node 53 and the feedback transistor 70.
In FIG. 9, reference symbol/RST represents an initial-condition-reset signal entered into the input terminal 50. This input terminal 50 is connected to the transistor 51 which is constituted by a P-channel transistor. Furthermore, the inverter 55 comprises a P-channel transistor 55a connected to the electric power source Vcc and an N-channel transistor 55b connected to the ground, the P-channel transistor 55a and the N-channel transistor 55b being connected in parallel with each other. Moreover, a set & reset circuit 71 comprises a NAND circuit 71a having two input terminals receiving signals B and C whose voltage levels cannot be univocally determined at the moment immediately after the electric power unit is turned on and a NOR circuit 71b having two input terminals receiving an output signal of the NAND circuit 71a and the output signal of the inverter 55. Using a high-level output of the inverter 55 as an initial setting signal makes the NOR circuit 71b of the set & reset circuit 71 generate a low-level output, thereby performing an initial setting of the operational condition of the internal circuit of the semiconductor integrated circuit.
However, such an initial value setting circuit proposed above is still defective in that the initial setting of the internal circuit cannot be performed in the event of momentary power failure or when the electric power unit is quickly turned on immediately after the electric power unit is once turned off. The reasons are explained as follows.
When the internal circuit is in a condition where the initial setting is reset, the output node 53 receives electric charges from the electric power source Vcc in response to the turning-on of the feedback transistor 70 as described above. Thus, the voltage level of the output node 53 is in a high level, while the output of the inverter 55 is in a low level. Therefore, the initial setting signal is reset. If the electric power unit is turned off in this condition, the voltage value of the electric power source Vcc is reduced to 0 v. Thus, electric charge stored in the capacitor 52 is discharged through the feedback transistor 70 to the electric power source, and the voltage level of the output node 53 is lowered. However, when the voltage level of the output node 53 is reduced down to a threshold voltage Vt of the feedback transistor 70, the feedback transistor 70 is turned off. Hence, the voltage level of the output node 58 is not equalized to 0 v, and the threshold voltage Vt is held. The electric charges forming such a residual voltage Vt are gradually leaked from the capacitor 52 with elapsing time. Then, the voltage of the output node 53 will be shortly equalized to 0 v.
If the electric power unit is subsequently turned on under such a condition as is so in an ordinary operation, the output signal of the inverter 5S becomes a high level. More specifically, the electric power source Vcc is applied through the P-channel transistor 55a of the inverter 55 to situate the inverter 55 in a high-level condition. Thus, the initial setting signal is output.
On the other hand, in the event of momentary power failure or when the electric power unit is quickly turned on after a very short break, the voltage level of the output node 53 is still maintained at a value substantially the same as the threshold voltage Vt. Meanwhile, the output terminal of the inverter 55 is connected through the N-channel transistor 55b to the ground level; thus, the voltage level of the output terminal of the inverter 55 is in a ground level. If the voltage value of the electric power source Vcc starts increasing from 0 v under this condition, the feedback transistor 70 will be turned on at the moment that the voltage value of the electric power source Vcc exceeds the threshold voltage Vt of the feedback transistor 70. Hence, electric charge is supplied from the electric power source Vcc to the output node 53. The voltage level of the output node 53 increases up to the voltage value of the electric power source Vcc as shown in FIG. 10 and becomes a high level. Consequently, in the inverter 55, the P-channel transistor 55a is turned off and the N-channel transistor 55b is turned on, thereby maintaining an output of low level. Thus, the initial setting signal (which should be inherently obtained as a high-level output signal, as shown by an alternate long and short dash line in FIG. 10) cannot be obtained. Accordingly, it is impossible to perform the initial setting of the internal circuit of the semiconductor integrated circuit in the special occasions such as momentary power failure or quick turning-on of electric power unit after a very short break.
According to the above initial value setting circuit, the output node 53 is in a low level in the initial condition and is changed to a high level in response to the reset operation. It is of course possible to replace this circuit by another type initial value setting circuit characterized in that the output node 53 is in a high level in the initial condition and is changed to a low level in response to the reset operation. However, adoption of such an initial value setting circuit will not yet effective to eliminate the problems encountered in the above-described initial value setting circuit, as long as it includes the above-described feedback transistor.